1. Field of the Invention
This disclosure relates to a method of forming contact pads of a semiconductor device, and more particularly, to a method of forming self-aligned contact (SAC) pads connected to source regions and drain regions of a semiconductor memory device.
2. Description of the Related Art
In accordance with the increase in storage capacity of semiconductor memory devices, especially DRAM, 256 Megabit DRAM are now commonly used and Gigabit DRAM is being prepared for mass production. For these high capacity devices and others like them, various layouts for memory cells have been suggested in order to decrease the design rule. Presently, straight type layouts and non-straight type layouts are widely used as layouts of active regions in memory cells. Examples of non-straight type layouts are disclosed in U.S. Pat. Nos. 5,194,752, 5,305,252, and 6,031,262.
FIG. 1 is a layout diagram illustrating non-straight type active regions and word lines of a conventional semiconductor DRAM device. Referring to FIG. 1, a plurality of non-straight type active regions 10 having identical patterns are repetitively arranged. Two of the word lines 15, which are formed by gate line structures across a single active region 10, divide the active region 10 into three parts. The outer portions A of the active region 10 are source regions and the central portion B is a common drain region. The source regions A are connected to a lower capacitor electrode (not shown) via a storage node contact pad (not shown) and the common drain region B is connected to a bit line (not shown) via a bit line contact pad (not shown).
A storage node contact pad and a bit line contact pad (contact pad) are formed between adjacent gate line structures 15. The contact pad is formed inside an interlayer insulating layer between adjacent gate line structures 15. A self-aligned etching process is used to form the contact pad. One example of the etching process will be described as follows.
First, an interlayer insulating layer is formed of silicon oxide over the entire surface of a semiconductor substrate. Gate electrode structures 15, which act as word lines, have been formed on the surface of the semiconductor substrate. Covering the upper surface and side of each gate electrode structure is a hard mask and a spacer composed of silicon nitride. Source regions A and a common drain region B (source/drain regions) have also been formed in the semiconductor substrate.
Next, contact holes exposing the source/drain regions A and B are formed, using a photolithography process. That is, a photo-resist is coated on the interlayer insulating layer, exposed by using a photo-mask on which a predetermined pattern is formed, and is developed so as to form a photo-mask pattern. Contact holes are generated by etching the interlayer insulating layer using the photo-mask pattern as an etching mask. Then, the contact holes are filled with conductive materials. Contact pads are formed by separating nodes from the conductive materials by a method such as etch back. A SAC pad forming method is conventionally used to form the contact pads.
FIG. 2A is a layout diagram illustrating a conventional photo-mask pattern used in a process of pattering contact holes for forming contact pads. Referring to FIG. 2A, the photo-mask pattern is a contact type pattern, which has light transmissive regions where contacts are to be formed and light-blocking regions elsewhere. FIG. 2B is a layout diagram illustrating contact holes formed over interlayer insulating layers 20 by using the photo-mask pattern shown in FIG. 2A. Referring to FIG. 2B, only source/drain regions A and B are exposed by the contact holes formed in the interlayer insulating layers 20.
When a conventional photo-mask having a contact type pattern is used in the process of patterning contact holes for forming contact pads, it is possible to directly form contact holes by etching only the necessary parts. Also, it is possible to forego a planarization process, such as chemical mechanical planarization (CMP), after forming an interlayer insulating layer because the light transmissive surface has a small area, thus reducing manufacturing costs and time.
However, it is not easy to use a photo mask having a contact type pattern in an actual process because exposing and etching processes can have limitations when the demand for increased integration requires that the intervals between contact holes be narrow. Especially when the intervals between contact holes and/or the size of contact holes are each less than 160 nm, it is difficult to precisely form contact holes and contact pads because of the limitations of exposing and etching processes. Also, it becomes necessary to conduct a CMP process on the interlayer insulating layer in order to form a fine pattern as the design rule decreases.
Embodiments of the invention address these and other disadvantages of the conventional art.